Staff Hsio/Ddr Bench Test Engineer (Tijuana)

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Engineering Group > Hardware Engineering

General Summary

This position is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs (System on Chip). The role focuses on defining and executing test methodologies and characterizing high‑speed SERDES interfaces such as PCIe, USB3, UFS, DP, MIPI(DSI,CSI), PLLs and other proprietary interfaces.

Responsibilities

• Develop and execute test methodologies and characterization for high‑speed SERDES interfaces (PCIe, USB3, UFS, DP, MIPI(DSI,CSI), PLLs, and other proprietary interfaces).
• Design and conduct characterization plans to optimize design parameters and validate electrical compliance across operating conditions.
• Lead first‑silicon bring‑up and debug to qualify designs fabricated at external foundries.
• Analyze parametric performance data and provide technical insights for...