Staff Design Verification Engineer

We are seeking a highly experienced and technically profound Design Verification Engineer to take on a technical leadership role in pre-silicon verification for complex, next-generation Application‑Specific Integrated Circuits (ASICs). This role is critical in driving verification excellence, setting technical direction, and mentoring local talent.

Key Responsibilities

• Verification Strategy & Ownership: Define, implement, and lead the overall verification strategy and test plan development (including functional, coverage, and performance) for complex digital ASIC blocks or full chips, ensuring robust quality before tape‑out.
• Advanced UVM Testbench: Architect, develop, and maintain advanced, reusable UVM‑based verification environments using SystemVerilog to enable constrained‑random and coverage‑driven verification.
• C/C++ Programming: Develop C/C++ test cases, firmware test cases for efficient hardware/software co‑verification via DPI‑C...