Found Description
SRAM Layout Engineer(LEADSOC Company)
JD:-
5–10 yrs in SRAM memory layout design
Strong in floor planning, power planning, area estimation.
Experience in physical verification.
Good knowledge of EM, latch-up, crosstalk, IR-drop, parasitics, matching, shielding.
Strong problem-solving in area, power, performance & verification.
Tools: Cadence Virtuoso (L/XL), Mentor Calibre.
Skilled in device matching, parasitic analysis, EM, isolation techniques.
Leadership, multitasking, team collaboration, and technical guidance.
Qualifications:
B. Tech/B. E/M. Tech/M. E
JD:-
5–10 yrs in SRAM memory layout design
Strong in floor planning, power planning, area estimation.
Experience in physical verification.
Good knowledge of EM, latch-up, crosstalk, IR-drop, parasitics, matching, shielding.
Strong problem-solving in area, power, performance & verification.
Tools: Cadence Virtuoso (L/XL), Mentor Calibre.
Skilled in device matching, parasitic analysis, EM, isolation techniques.
Leadership, multitasking, team collaboration, and technical guidance.
Qualifications:
B. Tech/B. E/M. Tech/M. E