Sr. Member Technical Staff - ESD and Latch-Up - HBM

As an SMTS/DMTS HBM ESD/Latch‑Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation, working across device, circuit, and packaging domains to solve reliability challenges and enable high‑performance memory.

Responsibilities

• Define end‑to‑end ESD and latch‑up architecture across base die, DRAM die, and interconnects
• Develop protection strategies for high‑speed I/O, TSV interfaces, and advanced packaging
• Establish ESD/LUP standards, rule decks, and sign‑off criteria
• Drive correlation between design assumptions, silicon validation, and field reliability
• Partner with foundry and packaging teams on system‑level ESD challenges

Minimum Qualifications

• MS or PhD in Electrical Engineering or related field, or equivalent...