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## SOC Timing EngineerApplylocations: Penang 15, Penang, Malaysiatime type: Full timeposted on: Posted Todayjob requisition id: R02767# **Job Details:**### ## **Job Description:*** As an STA design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.* Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.* Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure### ## **Qualifications:**Experience in Static timing analysis , and industry standard EDA tools like Primetime/PTPX- Good understanding of timing constraints, clocking, PVT etc- Should have tapeout experience including in latest technology 10nm or lower- BE/MS/Phd in Electronics/Electrical Engineering with 3+ Years' experience in physical design and timing closure/signoff-Ca...