Senior Verilog CPU Engineer — RISC-V & SoC

Bitdeer is seeking an experienced CPU/Processor Design Engineer to develop Verilog RTL for RISC‑V based CPU architectures and support verification closure activities. The role involves ensuring functional coverage, collaborating with verification and software teams to deliver high‑quality processor IP.

You will implement Verilog RTL for CPUs, support pre‑ and post‑silicon debugging, and contribute to design verification.