Senior Verification Engineer - RISC-V/UVM Expert

TechBiz Global GmbH is seeking a Senior Verification Engineer to ensure the correctness and functionality of complex digital designs in the development of RISC-V CPU cores. Candidates should possess a Master or PhD, with a minimum of 8 years of industrial experience and proficiency in SystemVerilog and UVM.

The role requires excellent communication and teamwork abilities and knowledge of scripting languages. This position is an exciting opportunity for growth in an innovative environment.