Senior UVM Verification Engineer for SoC/IP

COMBUILDER PTE LTD in Singapore is looking for a skilled Design Verification Engineer to develop and maintain UVM-based verification environments for SoC and IP-level verification.

The ideal candidate will have 4-6 years of experience, strong programming skills in SystemVerilog and Perl, and a good understanding of AMBA protocols. This role involves collaboration across teams, ensuring design validity through comprehensive testing and analysis.