Senior SoC Verification Engineer — UVM/RTL & Post‑Silicon

TetraMem in Singapore seeks a senior verification engineer to define and implement detailed test plans for SoC design verification. You will build automation infrastructure and reusable testbenches for both block and system levels, driving coverage and regression strategies.

You will collaborate with design engineers to debug simulations, support post-silicon validation, and mentor junior engineers, contributing to rapid verification with strong leadership in a startup-minded environment.