Senior RTL Design Engineer (ASIC)

Job Title:

Senior RTL Design Engineer (ASIC/SoC)
(with

DDR/LPDDR/MIPI exp)

Location : Bangalore, Indi
aExperience : 4+ Year
sNotice Period : 30–45 Days (Preferred

)
Role Overvie
w:We are looking for a highly skilled and motivate d ASIC RTL Design Engine er to join our team in Bangalore. You will be responsible for th e microarchitectu re, design, and implementation of complex digital IP blocks and subsystems. The ideal candidate will have strong expertise in high-speed interface protocols and a proven track record of delivering high-quality RTL within the ASIC/SoC design flo

w.
Key Responsibilit
iesMicroarchitecture Definit
ionRTL Implementat
ionProtocol Experti s e: DDR/LP DDR a nd M IPI protoco
ls.Design Quali ty: Perform RTL quality checks, including Linting, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) analys
is.Timing Clos

ure
Mandatory Skills & Experi
enceExperie nce: 4+ y...