Senior Principal SOC Design Engineer

Responsibilities

MaxLinear is seeking a Senior Principal SOC Design Engineer to join our VLSI group. You will be responsible for pre‑silicon RTL coding of block, subsystem and top level SOC integration. With deep understanding of design architecture and meticulous attention to details, you will develop robust and reusable code and ensure VHDL or Verilog implementation enables readiness for verification, synthesis, DfT and low‑power insertion. In this role, you will focus on:

• Pre‑silicon RTL coding of block, IP and top level SOC integration
• Develop reusable RTL code, using generic and modular coding style
• Contribute to verification plan from specification and in coordination with architects
• Collaborate on timing constraints, testability and insertion of low‑power structures such as power gating, isolation and retention sequential elements
• Own linting, CDC, RDC and collaborate with verification team and physical ...