Senior Physical Design Engineer — 5nm Transceivers

Astera Labs in Singapore is seeking a Senior Physical Design Engineer to take ownership of physical implementation from RTL to GDSII targeting TSMC's 5nm and 3nm nodes. In this role, you will lead initiatives ensuring timing and power closure for ultra-high-speed designs and tackle challenges with advanced nodes.

The ideal candidate will have a degree in Electrical Engineering and over 4 years of experience in physical design. The position offers the opportunity to work with cutting-edge technologies and a collaborative environment.