Senior PHY Design Engineer

Key Responsibilities:

1. Circuit Design & Development.

• Design high-speed analog circuits for DDR PHY interfaces (DDR4/DDR5/LPDDR5/6).
• Key modules: PLLs, DLLs, TX/RX channels, ODT (On-Die Termination), equalizers (CTLE/DFE), voltage regulators.
• Optimize power, performance, area (PPA), and signal integrity (SI).

2. Signal/Power Integrity (SI/PI) Analysis.

• Model and simulate channel losses, crosstalk, jitter, and eye diagrams.
• Ensure compliance with JEDEC standards (e.g., DDR5-6400 MT/s).
• Design impedance-matching networks and noise-suppression circuits.

3. Process Technology Adaptation.

• Implement designs in advanced nodes (FinFET, 7nm/5nm and below).
• Address PVT (Process-Voltage-Temperature) variations and reliability challenges (TDDB, EM/IR).
• Collaborate with layout engineers on floor planning, matching, and parasitic extraction.