Senior Memory Verification Engineer - Lead Mixed-Signal DRAM

Link-Worldwide is seeking a Senior Design Verification Engineer in Mexico, Jalisco, to work on advanced DRAM and emerging memory products. You will collaborate with innovative teams, enhancing verification methodologies and driving projects in a dynamic environment.

The ideal candidate will possess a strong understanding of CMOS design and experience in mixed-signal verification tools. Leadership skills and effective communication are essential to mentor junior engineers and work collaboratively across teams.