Senior IP / Subsystem Pre-silicon Validation Engineer

Role Summary

We are looking for an experienced Senior Validation Engineer to lead the functional verification and validation of complex SoC/IP designs. The ideal candidate will be responsible for defining the verification strategy, developing comprehensive verification plans, driving UVM-based verification environments, and ensuring high-quality silicon through thorough functional validation.

Key Responsibilities

• Drive the overall functional verification strategy for IP and SoC projects from planning to sign-off.
• Develop comprehensive verification plans based on design specifications, architecture documents, and customer requirements.
• Define verification methodologies, coverage goals, and regression strategies to achieve verification closure.
• Design, develop, and maintain SystemVerilog/UVM verification environments, reusable verification components, and testbenches.
• Create directed and constrained-random test cases...