Senior IC Package Design Engineer – High-Speed SerDes

Link-Worldwide is seeking an experienced Integrated Circuit Package Design Engineer located in Mexico, Jalisco, Región Centro. This role involves designing complex flip-chip-BGA packages crucial for high-speed SerDes, collaborating with a global R&D team, and managing projects from concept to manufacturing.

The ideal candidate should possess over 8 years of experience in package design, strong knowledge of signal and power integrity, and proficiency with Cadence APD. Join us in advancing industry-leading ASICs for areas such as AI, networking, and 5G.