Senior Ic Package Design Engineer: High‐Speed Serdes Packaging

Link-Worldwide in Mexico is seeking an Integrated Circuit Package Design Engineer to design complex flip-chip-BGA packages for cutting-edge ASICs. You will work with a worldwide R&D team to innovate designs for AI, networking, HPC, and 5G, applying your extensive experience in high-speed SerDes.
The role demands at least 8 years in relevant design, strong organizational skills, and proficiency with Cadence APD or similar tools. Join a dynamic team and contribute to transformative technologies on a global stage.
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