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Senior Engineer/ Engineer (Integration - Yield)

Vanguard International Semiconductor Corporation (VIS)

singapore, singapore, Singapore Full-time July 08, 2026

Found Description

Job Purpose

To liaise with module engineers on defect excursion control

To drive for defect reduction and yield improvement activities

Job Description
  • Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operati
  • Train and certify YE Associate Engineers on recipe creation and defect source knowledge
  • Maintain and enhance internal SOP/OCAP and involve in internal;/external audit
  • Operate FIB/SEM/EDX/OM for inline failure analysis
  • Operate and create recipes in Brightfield, Darkfield and other defect inspection tool
  • Perform partition analysis on defect source and detailed reports on issues
  • Build and develop defect source library.
  • Track inline defect performance by layer/process tool/chamber on weekly basis
  • Perform killer ration analysis
  • Perform defect characterization by process tools
  • Continuous improvement activi...

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