Senior Dram Layout & Ip Verification Lead

Link-Worldwide in Mexico, Jalisco is seeking a DRAM Design Engineer to transform schematics into layouts for fabrication reticules.The role involves designing IP layouts, verifying layouts for quality, and ensuring timely project delivery.The ideal candidate should have a Bachelor's in Electrical or Electronics Engineering and at least 3 years of experience in advanced CMOS layout design, with strong problem-solving skills and proficiency with Cadence tools.
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