Senior Design Verification Engineer (PCIe)

Responsibilities

• Develop and execute verification plans for PCIe IP/SoC designs.
• Build and maintain SystemVerilog/UVM verification environments.
• Develop directed and constrained-random test cases to achieve coverage goals.
• Verify PCIe protocol (Gen3/Gen4/Gen5), including protocol compliance and functional correctness.
• Debug RTL and simulation issues, analyze waveforms, and support verification closure.
• Collaborate with design, architecture, and validation teams.

Requirements

• Bachelor's degree in Electrical/Electronics/Computer Engineering or related field.
• Strong hands‑on experience with SystemVerilog, UVM, and PCIe protocol verification .