Senior Design Verification Engineer at Astera Labs

Elevate your career as a Senior Design Verification Engineer with Astera Labs in Canada. This role focuses on utilizing UVM and C/C++ for advanced SoC verification tasks.
Astera Labs is seeking an experienced engineer to contribute to complex silicon products for Server, Storage, and Networking applications. You will leverage your expertise in System Verilog and verification methodologies to create and implement test plans, develop verification infrastructure, and ensure robust performance. Collaboration with RTL designers is essential for debugging, making this position a vital part of our innovative team.
Key Responsibilities:
• Integrate C/C++ in System Verilog environments using DPI/PLI
• Automate verification infrastructure with scripting tools like Perl/Python
• Develop test-plans and sequences in UVM
• Collaborate with RTL designers to debug failures
• Create user-controlled random constraints for testing
Requirements:
• Bachelor’s in Electrical Engine...