Senior ASIC Verification Engineer (UVM, Formal)

A leading technology firm in Singapore is looking for a design verification engineer. In this role, you will join a dedicated team to develop advanced verification methodologies, aiming for zero defects across complex designs. Applicants should ideally have experience in UVM verification and a relevant degree, with 8 years of experience preferred, though exceptional fresh graduates will also be considered. Knowledge in video processing is a plus, alongside strong programming skills.
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