Senior ASIC Verification Engineer - SystemVerilog/UVM

A leading technology firm based in Ottawa seeks a Senior ASIC Verification Specialist to join their experienced team. You will be responsible for verifying large ASIC designs, employing SystemVerilog and UVM methodologies to ensure functionality and performance. The ideal candidate should have over 7 years of ASIC verification experience and be skilled in Verilog, SystemVerilog, and advanced architectural knowledge. This role offers a competitive salary ranging from $120,000 to $170,000, alongside a bonus and benefits package.
#J-18808-Ljbffr