Senior ASIC Verification Engineer at Synopsys

Elevate your career as a Senior ASIC Design Verification Engineer at Synopsys, focusing on cutting-edge High Bandwidth Memory products. Utilize your expertise in SystemVerilog and UVM methodologies to advance technology.
At Synopsys, you will develop and implement comprehensive verification plans while debugging and analyzing complex ASIC designs. With a minimum of 10 years in digital design and verification, you're driven to innovate and solve complex challenges. Join a collaborative team dedicated to high-performance projects that revolutionize computing.
Key Responsibilities:
• Develop comprehensive verification plans for HBM ASIC designs
• Write advanced testcases using SystemVerilog and UVM
• Debug complex testbench and design issues with teams
• Automate verification processes with Python or Perl scripting
• Review design specifications and provide constructive feedback
Requirements:
• Bachelor’s or Master’s in Electrical Engineering
• 10+ years of d...