Senior ASIC Verification Engineer at Synopsys

Enhance your ASIC verification skills at Synopsys as a Senior Engineer. Drive innovation in HBM products and leverage your expertise in digital design.
In this senior role, you will utilize your 10+ years of digital design and verification experience. Your focus will be on developing comprehensive verification plans and employing SystemVerilog and UVM methodologies. Collaborating with design teams, you will debug complex issues and automate workflows using scripting languages like Python or Perl.
Key Responsibilities:
• Develop comprehensive verification plans for HBM products
• Write advanced testcases with SystemVerilog and UVM
• Debug complex testbench and design issues collaboratively
• Automate verification flows using Python or Perl
• Review design specifications and provide feedback
Requirements:
• Bachelor’s or Master’s in Electrical Engineering
• 10+ years of digital design/verification experience
• Proven skills in SystemVerilog and UVM
• S...