Senior ASIC Implementation Engineer - Synthesis & Timing

Lancesoft Malaysia in Penang seeks an experienced RTL/PD engineer to drive synthesis, timing closure, and DFT integration for complex full-chip designs. You will collaborate with RTL, physical design, and DFT teams to preempt issues and deliver reliable netlists on schedule.

The role requires hands-on work with DC/Genus/Fusion Compiler, PrimeTime/Tempus, and Formality/Conformal, plus scripting in Perl, Python or TCL.