Semiconductor Packaging Engineer

Senior Engineer - CMOS & Metallization Test Structure Design and Layout

Qualifications

• 8+ years of experience in flip‑chip BGA package design with high‑speed SerDes (BSEE or similar field) or 6+ years of experience with MSEE or similar field.
• Experience with Cadence APD (Allegro Package Designer) or equivalent tools.
• Knowledge of package‑level signal integrity and power integrity.
• Self‑management and organizational skills.

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Function

Consulting and Engineering

Industries

Semiconductor Manufacturing