Found Description
8 years of experience in flip-chip-BGA package design with high-speed SerDes (BSEE or similar field) or 6 years of experience with MSEE or similar field. Experience with Cadence APD (Allegro Package Designer) or equivalent tools. Knowledge of package-level signal integrity and power integrity. Self-management and organizational skills.
Ready to Apply?
Submit your application for Semiconductor Packaging Engineer at Global Connect Technologies
Apply Now