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Remote RTL Design Engineer: ASIC Power & Performance

BairesDev

puebla de zaragoza, puebla de zaragoza, Mexico Full-time June 14, 2026

Found Description

BairesDev is looking for an experienced RTL Design Engineer to design advanced logic for ASIC chips. This 100% remote position requires proficiency in Verilog and SystemVerilog, along with a strong background in digital architecture and ASIC design.

Successful candidates will contribute to high-performance projects, engage with cross-functional teams, and enjoy flexible hours and excellent compensation. Join our global team and thrive in a supportive environment focused on your growth!

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