Principal RTL Design Engineer

Job Overview

The Mixed Signal Development Group delivers high‑performance analog, digital, and mixed‑signal IP to various divisions within Microchip. Leveraging advanced CMOS processes, the team designs mixed‑signal integrated circuits for wireline applications, enabling seamless connectivity between Microchip products and the external world. As a member of the group, you will work closely with architects, digital design engineers, verification engineers, firmware engineers, and cross‑functional teams.

Responsibilities

• Participate in the full ASIC design cycle, including design, verification, backend implementation, silicon bring‑up, and debugging.
• Design RTL using Verilog/SystemVerilog, integrate IP blocks, and implement supporting logic (clock/reset, JTAG, DFT, SRAMs, etc.).
• Run clock‑domain crossing (CDC) analysis, lint checks, and power simulations.
• Work with verification teams or participate in verification, review, op...