Found Description
Join Microchip's Mixed Signal Development Group as a Principal RTL Design Engineer, focusing on high-performance analog and digital circuit design. Engage in a dynamic embedded environment, requiring expertise in Verilog/SystemVerilog for ASIC development.
In this key role, you will drive the full ASIC design cycle, from initial design through verification to silicon bring-up. Collaborate effectively with a range of professionals, including architects, digital design engineers, and firmware engineers, contributing to integrated circuit solutions. Your efforts will ensure robust and efficient designs across wireline applications.
Key Responsibilities:
• Participate in full ASIC design cycle activities
• Design RTL using Verilog/SystemVerilog and integration
• Perform clock-domain crossing analysis and power simulations
• Collaborate with verification teams for effective debugging
• Work with backend team on timing closure and synth...
In this key role, you will drive the full ASIC design cycle, from initial design through verification to silicon bring-up. Collaborate effectively with a range of professionals, including architects, digital design engineers, and firmware engineers, contributing to integrated circuit solutions. Your efforts will ensure robust and efficient designs across wireline applications.
Key Responsibilities:
• Participate in full ASIC design cycle activities
• Design RTL using Verilog/SystemVerilog and integration
• Perform clock-domain crossing analysis and power simulations
• Collaborate with verification teams for effective debugging
• Work with backend team on timing closure and synth...
Ready to Apply?
Submit your application for Principal RTL Design Engineer at Microchip at FHLB Des Moines
Apply Now