Principal Engineer, VLSI Design Engineering (SOC Verification, System Verilog, UVM)

Job responsibilities:  

• 8+ Years of relevant Logic Verification experience 

• Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC 

• Create verification environment using UVM methodology 

• Create reusable bus functional models, monitors, checkers and scoreboards 

• Drive functional coverage driven verification closure. 

• Work with architects, designers, and post-silicon teams 

• Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions 

• Development of tools for Design and Verification support 

• Debug failures and root-cause it by interact...