Principal Engineer, ASIC Development Engineering (SOC Verification, System Verilog, Flows, Python, Scripting) with 8 to 12 years of experience

• Providing technical leadership and expertise to define requirements for framework through programming/scripting of verification and emulation flows.
• Partnering with ASIC engineers to deploy and support framework for technologies like advanced verification environment configuration and management.
• Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies.

• BE or MS degree in Electrical Engineering or Computer Engineering, with 8+ years of experience.
• Understanding C, SystemVerilog UVM, coverage driven verification methodology especially testplan creation and constructs of testbench architecture. 
• Scripting and regression suite development experience using Python, TCL and Perl
• Excellent debugging and problem-solving skills with simulation and emulation environments.

Skills Required: