Found Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
+ Prior 7-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
+ Should possess intimate knowledge of DFT insertion flows
+ Basic scan chain insertion using synthesis or other software tools
+ Experience in compression scan insertion, LBIST and other scan technologies
+ Intimate knowledge of memory build-in self-test (MBIST)
+ Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
+ Debug and Analysis of failures to improve fault coverage
+ Verification of ATPG testbenches and debugging root cause of simulation mis-compares
+ Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
+ Knowledge of timing analysis and equivalency checks would be added bonus
+ Ability to work in ...
+ Prior 7-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
+ Should possess intimate knowledge of DFT insertion flows
+ Basic scan chain insertion using synthesis or other software tools
+ Experience in compression scan insertion, LBIST and other scan technologies
+ Intimate knowledge of memory build-in self-test (MBIST)
+ Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
+ Debug and Analysis of failures to improve fault coverage
+ Verification of ATPG testbenches and debugging root cause of simulation mis-compares
+ Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
+ Knowledge of timing analysis and equivalency checks would be added bonus
+ Ability to work in ...
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