Found Description
Responsible for ensuring timing closure of complex ASIC/SoC designs by performing static timing analysis throughout the design cycle. Collaborate with RTL, synthesis, physical design, DFT, and signoff teams to optimize timing, power, and area while meeting performance targets.
Experience: 3+ years
Key Responsibilities
- Perform block-level and full-chip static timing analysis (STA) using industry-standard EDA tools.
- Analyze setup, hold, recovery, removal, and clock gating timing violations.
- Drive timing closure across synthesis, place-and-route (PnR), and signoff stages.
- Develop and validate timing constraints (SDC), timing exceptions, and clock definitions.
- Perform timing debugging, root‑cause analysis, and recommend RTL or physical design optimizations.
- Collaborate with Physical Design engineers to optimize timing through placement, CTS, buffering, and routing improvements.
- Analyze cross‑t...