Found Description
Responsibilities
- Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full‑chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths.
- Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools.
- Participate in PPA (Power, Performance, Area) and yield optimization, including related tool development and flow improvement.
Requirements
- Proficient in the complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.); strong expertise in STA analysis methods and flows; familiar with DC or FC synthesis processes.
- Experience in top‑level PR/PI/PV/BUMP or ESD planning is a plus; familiarity with signoff standards for advanced process nodes is preferred; proven tape‑out experience with ultra‑low‑...