Found Description
Elevate your design expertise with Infosys as a Memory Layout Engineer in Vancouver BC. Collaborate on innovative memory architectures to create optimal layouts and push boundaries in technology.
In this role, you will engage with Registers, Memory Arrays, and circuit design teams to craft exceptional memory layouts. We seek candidates with a minimum of five years in Compiler/Custom Memory Layout design, alongside strong skills in FinFET technology and physical verification. Your experience will drive seamless integration and innovation in our projects.
Key Responsibilities:
• Collaborate with design teams to create efficient memory layouts
• Design memory leafcell layout libraries from scratch
• Integrate top-level architecture with optimized performance
• Conduct physical verification and debug DRC, LVS, and ERC flows
• Ensure compliance with boundary conditions during layout design
Requirements:
• Minimum 4 years of Information Technology experience
• B...
In this role, you will engage with Registers, Memory Arrays, and circuit design teams to craft exceptional memory layouts. We seek candidates with a minimum of five years in Compiler/Custom Memory Layout design, alongside strong skills in FinFET technology and physical verification. Your experience will drive seamless integration and innovation in our projects.
Key Responsibilities:
• Collaborate with design teams to create efficient memory layouts
• Design memory leafcell layout libraries from scratch
• Integrate top-level architecture with optimized performance
• Conduct physical verification and debug DRC, LVS, and ERC flows
• Ensure compliance with boundary conditions during layout design
Requirements:
• Minimum 4 years of Information Technology experience
• B...