W

Memory Layout

Weekday AI

Bengaluru, Karnataka, India Full time July 09, 2026

Found Description

๐—ง๐—ต๐—ถ๐˜€ ๐—ฟ๐—ผ๐—น๐—ฒ ๐—ถ๐˜€ ๐—ณ๐—ผ๐—ฟ ๐—ผ๐—ป๐—ฒ ๐—ผ๐—ณ ๐˜๐—ต๐—ฒ ๐—ช๐—ฒ๐—ฒ๐—ธ๐—ฑ๐—ฎ๐˜†'๐˜€ ๐—ฐ๐—น๐—ถ๐—ฒ๐—ป๐˜๐˜€

๐—ฆ๐—ฎ๐—น๐—ฎ๐—ฟ๐˜† ๐—ฟ๐—ฎ๐—ป๐—ด๐—ฒ: ๐—ฅ๐˜€ ๐Ÿด๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ - ๐—ฅ๐˜€ ๐Ÿญ๐Ÿด๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ (๐—ถ๐—ฒ ๐—œ๐—ก๐—ฅ ๐Ÿด-๐Ÿญ๐Ÿด ๐—Ÿ๐—ฃ๐—”)

Experience: 3+ yrs

Location: Bengaluru

Job Type: Full-time

We are looking for a skilled Memory Layout Engineer with hands-on experience in advanced semiconductor technology nodes to design and optimize high-performance memory layouts. This role is ideal for professionals with expertise in Memory Layout, TSMC 2nm & TSMC 3nm technologies, DRC, and LVS, along with a strong understanding of physical design methodologies and layout optimization.

As a Memory Layout Engineer, you will be responsible for developing accurate and manufacturable memory layouts while ensuring compliance with foundry design rules and quality standards. You will collaborate closely with circuit designers, physical design engineers, verification teams, and process engineers to deliver optimized memory macros that ...

Ready to Apply?

Submit your application for Memory Layout at Weekday AI

Apply Now