Lead DRAM IP Layout Engineer – Design & Mentorship

Link-Worldwide in Mexico is seeking a skilled layout design engineer with over 4 years of experience in advanced CMOS processes. The role focuses on designing and developing IP layouts for DRAM chips, ensuring quality in layout verification and delivering projects on time.

The ideal candidate will demonstrate strong leadership abilities, planning skills, and expertise in Cadence tools. You will work closely with global teams to enhance project success and guide junior engineers.