U

IC Package Design Engineer

UST Malaysia

bayan lepas, penang, Malaysia Full-time July 12, 2026

Found Description

Responsibilities

  • Executing high density package layout designs across client’s product portfolios (Test Chips, CPUs, Chipsets, SoC designs, Test Vehicles and more)
  • Perform DRC checks , unconnected pins and dangling trace/vias and fix the design accordingly.
  • Perform design self-check based on the design review checklist provided and fix the design accordingly.
  • Perform design cleanup with PLA tools . (Depend on the accessibility of the PLA tools)
  • Full package design including all/partial interfaces assignment as well as power assignment according to schematic that provided. Might include the component placement and constraint setting as well as other package design related request.
  • Using the Mentor Graphics Xpedition PCB software to design the substrate in compliance with existing design rules, electrical requirements and processes.
  • Must understand various interface requirement like DDR/PCIe/S...

Ready to Apply?

Submit your application for IC Package Design Engineer at UST Malaysia

Apply Now