E5_MTS_SMTS NAND Design Rule Engineer in Process Integration

As a E5/MTS/SMTS NAND Design Rule / Process Integration engineer, your role is to support the development and high-volume manufacturing of advanced 3D NAND technologies, driving design-rule and PDK deliverables, partnering closely across process integration and design organizations, and ensuring quality, documentation, and timely execution across R&D and production programs.

Responsibilities

• Lead the release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for both R&D and production designs.
• Own program execution and milestones from kickoff through end-of-life.
• Partner with stakeholders across Array & CMOS Process Integration, Devices, Layout & Design, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.
• Ensure high quality and documentation for Design Rule Checks (DRCs) and drive timely disposition of deviat...