Found Description
Role Summary
The DSP/Digital Engineer develops FPGA and digital processing pipelines for ultrasound acquisition and beamforming, enabling high-throughput, low-latency data paths from front‑end electronics to imaging/analysis software. The role covers RTL architecture, timing closure, interfacing to ADCs/DACs and memory, and verification.Key ResponsibilitiesArchitect and implement FPGA/RTL modules (VHDL/Verilog/SystemVerilog) for data capture, digital beamforming primitives, filtering, and high-speed I/O.Define and integrate high-speed interfaces (LVDS, JESD204B/C, PCIe, DDRx); implement clocking/PLL schemes, resets, and CDC strategies to meet timing.Develop verification artifacts (testbenches, simulation, coverage) and support on‑target validation with structured bring‑up procedures.Collaborate with hardware and software teams on partitioning, throughput/latency budgets, and DMA/driver integration.Create performance tests, profiling tools, and diagnostics; support field/system inves...
The DSP/Digital Engineer develops FPGA and digital processing pipelines for ultrasound acquisition and beamforming, enabling high-throughput, low-latency data paths from front‑end electronics to imaging/analysis software. The role covers RTL architecture, timing closure, interfacing to ADCs/DACs and memory, and verification.Key ResponsibilitiesArchitect and implement FPGA/RTL modules (VHDL/Verilog/SystemVerilog) for data capture, digital beamforming primitives, filtering, and high-speed I/O.Define and integrate high-speed interfaces (LVDS, JESD204B/C, PCIe, DDRx); implement clocking/PLL schemes, resets, and CDC strategies to meet timing.Develop verification artifacts (testbenches, simulation, coverage) and support on‑target validation with structured bring‑up procedures.Collaborate with hardware and software teams on partitioning, throughput/latency budgets, and DMA/driver integration.Create performance tests, profiling tools, and diagnostics; support field/system inves...