Found Description
Responsibilities
- Implement DFT including: at-speed scan, LBIST, MBIST, JTAG, self-test, and IP integration
- Work closely with synthesis, static timing, and layout engineers to optimize DFT circuits.
- Generate and verify Test vectors before chip tapeout.
- Support test vector bring up and debug on ATE.
- Support silicon failure analysis, diagnostics, and yield improvement.
- Create innovative DFT solutions to solve testability problems and improve coverage.
- Automate DFT & test vector generation flows.
- Deep understanding of DFT concepts such as at-speed scan, LBIST, MBIST, JTAG, self-test, analog DFT, and more.
- Experience with DFT tools such as Tessent, TetraMax, etc.
- Scan Insertion and scan compression experience.
- Memory BIST insertion and verification experience.
- Logic BIST design and debug experience.
- Experience with A...