Design for Test (DFT) Engineer – RTL & Test Chip Architecture

<b>Design for Test (DFT) Engineer RTL & Test Chip Architecture</b> <p data-end="243" data-start="109"><b>Location:</b> Bengaluru, India<br data-end="142" data-start="139" /> <b>Work Mode:</b> Onsite<br data-end="166" data-start="163" /> <b>Experience:</b> 5 12 Years<br data-end="195" data-start="192" /> <b>Industry:</b> Semiconductor / VLSI / ASIC Design</p> <b>Role Overview</b> <p data-end="806" data-start="272">We are looking for an experienced <b>Design for Test (DFT) Engineer</b> with expertise in <b>RTL-based DFT implementation, Test Chip Architecture, Scan Design, ATPG, MBIST, and silicon validation</b> for advanced ASIC and SoC designs. The role involves developing scalable DFT architectures, implementing test features at RTL, improving manu...