Found Description
Hiring – ASIC RTL Design Engineer (5+ Years Experience)
We are actively looking for experienced ASIC RTL Design Engineers to join our team.
Experience: 5+ Years
Location: Bangalore / Hyderabad
Required Skills:
Strong experience in ASIC RTL Design using Verilog/System Verilog
Solid understanding of So C Microarchitecture and RTL implementation
Hands-on experience with high-speed interface protocols such as MIPI and LPDDR
Experience in So C integration, RTL development, synthesis, lint, CDC, and timing analysis
Good understanding of ASIC design flow and methodology
Strong debugging, problem-solving, and communication skills
Preferred:
Experience working on complex So C/ASIC projects from microarchitecture to RTL sign-off
Familiarity with low-power design concepts and performance optimization
Interested candidates can share their resumes at .
Please share this opportunity with relevant candidates in your network.
We are actively looking for experienced ASIC RTL Design Engineers to join our team.
Experience: 5+ Years
Location: Bangalore / Hyderabad
Required Skills:
Strong experience in ASIC RTL Design using Verilog/System Verilog
Solid understanding of So C Microarchitecture and RTL implementation
Hands-on experience with high-speed interface protocols such as MIPI and LPDDR
Experience in So C integration, RTL development, synthesis, lint, CDC, and timing analysis
Good understanding of ASIC design flow and methodology
Strong debugging, problem-solving, and communication skills
Preferred:
Experience working on complex So C/ASIC projects from microarchitecture to RTL sign-off
Familiarity with low-power design concepts and performance optimization
Interested candidates can share their resumes at .
Please share this opportunity with relevant candidates in your network.