Asic dtco, timing and technology engineer

Company

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Responsibilities Work with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologies 5nm, 4nm … 2nm and beyond. Responsible for Spice simulations (Hspice/Finesim/Prime Sim/AFS/Spectre) for power and performance validation and STA sign off using PT/PT-SI and Tempus. Responsible for block level PPA analysis/implementation (RTL to GDS flow) for hard macros using FC Synthesis, FC Place and Route, Genus and Innovus. Responsible for design implementation of multiple blocks working with foundry DTCO team, EDA companies (partners), CAD team and IP team driving Fmax optimization, PPAY and cost improvements/reduction. Good execution knowledge. Contribution should improve design convergence process across the company, design PPAY and support new advanced process...